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may 2006 rev 5 1/31 1 m24512-w m24512-r 512 kbit serial i2c bus eeprom feature summary two-wire i 2 c serial interface supports 400 khz protocol supply voltage ranges: 1.8v to 5.5v (m24512-r) 2.5v to 5.5v (m24512-w) write control input byte and page write (up to 128 bytes) random and sequential read modes self-timed programming cycle automatic address incrementing enhanced esd/latch-up protection more than 1,000,000 write cycles more than 40-year data retention so8 (mw) 208 mil width tssop8 (dw) 8 1 8 1 so8 (mn) 150 mil width www.st.com
contents m24512-w, m24512-r 2/31 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.2 internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.9 write cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.10 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . 16 3.11 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.13 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.14 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.15 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
m24512-w, m24512-r contents 3/31 6 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
list of tables m24512-w, m24512-r 4/31 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. operating conditions (m24512 ? w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. operating conditions (m24512 ? r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. dc characteristics (m24512-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. dc characteristics (m24512-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. ac characteristics (m24512-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. ac characteristics (m24512-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. so8w ? 8 lead plastic small outline, 208 mils body width, package mechanical data . . . 25 table 16. so8n ? 8 lead plastic small outline, 150 mils body width, package mechanical data . . . 26 table 17. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . 27 table 18. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
m24512-w, m24512-r list of figures 5/31 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. so and tssop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. maximum r p value versus bus parasitic capacitance (c) for an i 2 c bus . . . . . . . . . . . . . 9 figure 5. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. write mode sequences with wc = 1 (data write inhibited). . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. ac measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. so8w ? 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . 25 figure 13. so8n ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . 26 figure 14. tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 27
summary description m24512-w, m24512-r 6/31 1 summary description these i 2 c-compatible electrically erasable pr ogrammable memory (eeprom) devices are organized as 64k x 8 bits. i 2 c uses a two-wire serial interface, comprising a bi-directional data line and a clock line. the devices carry a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and read/write bit (rw ) (as described in ta bl e 2 ), terminated by an acknowledge bit. when writing data to the memory, the device inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. in order to meet environmental requirements, st offers these devices in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 1. logic diagram table 1. signal names e0, e1, e2 chip enable sda serial data scl serial clock wc write control v cc supply voltage v ss ground ai02275b sda v cc m24512-w m24512-r wc scl v ss 3 e0-e2
m24512-w, m24512-r summary description 7/31 figure 2. so and tssop connections 1. see package mechanical section for package dimensions , and how to identify pin-1. 1 ai04035c 2 3 4 8 7 6 5 sda v ss scl wc e1 e0 v cc e2 m24512-w m24512-r
signal description m24512-w, m24512-r 8/31 2 signal description 2.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from serial clock (scl) to v cc . ( figure 4. indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of sy nchronization is not employed, and so the pull- up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 serial data (sda) this bi-directional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( figure 4. indicates how the value of the pull-up resistor can be calculated). 2.3 chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code. when not connected (left floating), these inputs are read as low (0,0,0). figure 3. device select code 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disabled to the entire memory array when write control (wc ) is driven high. when unconnected, the signal is internally read as v il , and write operations are allowed. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i
m24512-w, m24512-r signal description 9/31 2.5 supply voltage (v cc ) 2.5.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 7 and ta b l e 8 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10nf to 100nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.5.2 internal device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in ta bl e 7 and ta b l e 8 ). when v cc has passed the por threshold, the device is reset and is in standby power mode. 2.5.3 power-down at power-down (continuous decrease of v cc ), as soon as v cc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any inst ruction sent to it. during power-down, the device must be deselected and in the standby power mode (that is there should be no internal write cycle in progress). figure 4. maximum r p value versus bus parasitic capacitance (c) for an i 2 c bus ai01665b v cc c sda r p master r p scl c 100 0 4 8 12 16 20 c (pf) maximum rp value (k ? ) 10 1000 fc = 400khz fc = 100khz
signal description m24512-w, m24512-r 10/31 figure 5. i 2 c bus protocol table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0, e1 and e2 are compared against the respec tive external pins on the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1010e2e1e0rw table 3. most significant address byte b15 b14 b13 b12 b11 b10 b9 b8 table 4. least significant address byte b7 b6 b5 b4 b3 b2 b1 b0 scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
m24512-w, m24512-r device operation 11/31 3 device operation the device supports the i 2 c protocol. this is summarized in figure 5. . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization. the m24512 device is always a slave in all communication. 3.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not respond unless one is given. 3.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the stand-by mode. a stop condition at the end of a write command triggers the internal write cycle. 3.3 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 3.4 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low.
device operation m24512-w, m24512-r 12/31 3.5 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. following this, t he bus master sends the device select code, shown in table 2. (on serial data (sda), most significant bit first). the device select code consists of a 4-bit de vice type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into stand-by mode. table 5. operating modes mode rw bit wc (1) 1. x = v ih or v il . bytes initial sequence current address read 1 x 1 s tart, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 128 start, device select, rw = 0
m24512-w, m24512-r device operation 13/31 figure 6. write mode sequences with wc = 1 (data write inhibited) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120c page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
device operation m24512-w, m24512-r 14/31 3.6 write operations following a start condition the bus master sends a device select code with the read/write bit (rw ) reset to 0. the device acknowledges this, as shown in figure 7. , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if write control (wc ) is driven high. any write instruction with write control (wc ) driven high (during a period of time from the start condition until the end of the two address byte s) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 6. . each data byte in the memory has a 16-bit (two byte wide) address. the most significant byte ( ta b l e 3 . ) is sent first, followed by the least significant byte ( table 4. ). bits b15 to b0 form the address of the byte in memory. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition, the delay t w , and the successful completion of a write operation, the device?s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. during the internal write cycle, serial data (sda) is disabled internally, and the device does not respond to any requests. 3.7 byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 7. 3.8 page write the page write mode allows up to 128 bytes to be written in a single write cycle, provided that they are all located in the same ?row? in the memory: that is, the most significant memory address bits (b15- b7) are the same. if more bytes ar e sent than will fit up to the end of the row, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 128 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a noack. after each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition.
m24512-w, m24512-r device operation 15/31 3.9 write cycling the m24512-w and m24512-r devices are qualified at 1 m illion (1,000,000) write cycles, at 25c. caution: note that the m24512-w and m24512-r in so8wide package (mw) are offered with either the previous die qualified at 100.000 write cycl es or the new die (qualified at 1 million write cycles). the two dice are distinguised by their respective process letter: "v" for the previous die and " a" for the new die. please contact your nearest st sales office for more information. figure 7. write mode sequences with wc = 0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106c page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack
device operation m24512-w, m24512-r 16/31 figure 8. write cycle polling flowchart using ack 3.10 minimizing system de lays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 13. , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 8. , is: initial condition: a write cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the inte rnal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
m24512-w, m24512-r device operation 17/31 3.11 read operations read operations are performed independently of the state of the write control (wc ) signal. after the successful completion of a read operation, the device?s internal address counter is incremented by one, to point to the next byte address. 3.12 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 9. ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 3.13 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 9. , without acknowledging the byte. 3.14 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 9. the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h.
device operation m24512-w, m24512-r 18/31 figure 9. read mode sequences 1. the seven most significant bits of the device select code of a random read (in the 1 st and 4 th bytes) must be identical. 3.15 acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its stand-by mode. start dev sel * byte addr byte addr start dev sel data out 1 ai01105c data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
m24512-w, m24512-r initial delivery state 19/31 4 initial delivery state the device is delivered with all bits in the memory array set to 1 (each byte contains ffh). 5 maximum rating stressing the device outside the ratings listed in ta bl e 6 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020c (for smal l body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu c v io input or output range ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (2) 2. aec-q100-002 (compliant wi th jedec std jesd22-a114a, c1=100pf, r1=1500 ? , r2=500 ? ) ?4000 4000 v
dc and ac parameters m24512-w, m24512-r 20/31 6 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 10. ac measurement i/o waveform table 7. operating conditions (m24512 ? w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 85 c table 8. operating conditions (m24512 ? r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 9. ac measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
m24512-w, m24512-r dc and ac parameters 21/31 table 10. input parameters symbol parameter (1),(2) 1. t a = 25 c, f = 400 khz 2. sampled only, not 100% tested. test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z l (3) 3. e2,e1,e0: input impedance when the memory is selected (after a start condition). input impedance (e2, e1, e0, wc ) v in < 0.3v cc 30 k ? z h (3) input impedance (e2, e1, e0, wc ) v in > 0.7v cc 500 k ? t ns pulse width ignored (input filter on scl and sda) single glitch 100 ns table 11. dc characteristics (m24512-w) symbol parameter test condition min. max. unit i li input leakage current (scl, sda, e0, e1, e2) v in = v ss or v cc device in standby mode (1) 1. when the device is selected (after a start condition ), the ei inputs have a different input impedance, as defined in table 10. 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current (read) v cc = 2.5v, f c =400khz (rise/fall time < 30ns) 1ma v cc = 5.5v, f c =400khz (rise/fall time < 30ns) 2ma i cc0 supply current (write) during t w , 2.5v < v cc < 5.5v 5 (2) 2. characterized value, not tested in production. ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 2.5 v 2 a v in = v ss or v cc , v cc = 5.5 v 5 a v il input low voltage (scl, sda, wc ) ?0.45 0.3v cc v v ih input high voltage (scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v 0.4 v
dc and ac parameters m24512-w, m24512-r 22/31 table 12. dc characteristics (m24512-r) symbol parameter test condition min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in stand-by mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current (read) v cc =1.8v, f c = 400khz (rise/fall time < 30ns) 1ma i cc0 supply current (write) during t w , 1.8v < v cc < 5.5v 5 (1) 1. characterized value, not tested in production. ma i cc1 standby supply current v in = v ss or v cc , v cc = 1.8 v 2 a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7v cc v cc +1 v v ol output low voltage i ol = 0.7 ma, v cc = 1.8 v 0.2 v table 13. ac characteristics (m24512-w) symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t ch1ch2 t r clock rise time 300 ns t cl1cl2 t f clock fall time 300 ns t dh1dh2 (1) 1. sampled only, not 100% tested. t r sda rise time 20 300 ns t dl1dl2 (1) t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv (2) 2. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. t aa clock low to next data valid (access time) 200 900 ns t chdx (3) 3. for a restart condition, or following a write cycle. t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 5 or 10 (4) 4. for m24512-w devices whose package mark ing shows the process letter ?a? t w (max) = 5ms whereas for m24512-w devices whose pac kage marking shows the process letter ?v? t w (max) = 10ms ms
m24512-w, m24512-r dc and ac parameters 23/31 table 14. ac characteristics (m24512-r) symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 (1) 1. sampled only, not 100% tested. t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv (2) 2. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. t aa clock low to next data valid (access time) 200 900 ns t chdx (3) 3. for a restart condition, or following a write cycle. t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 10 ms
dc and ac parameters m24512-w, m24512-r 24/31 figure 11. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795c start condition
m24512-w, m24512-r package mechanical 25/31 7 package mechanical figure 12. so8w ? 8 lead plastic small outline, 208 mils body width, package outline 1. drawing is not to scale. table 15. so8w ? 8 lead plastic small outline, 208 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 2.03 0.080 a1 0.10 0.25 0.004 0.010 a2 1.78 0.070 b 0.35 0.45 0.014 0.018 c 0.20 ? ? 0.008 ? ? d 5.15 5.35 0.203 0.211 e 5.20 5.40 0.205 0.213 e 1.27 ? ? 0.050 ? ? h 7.70 8.10 0.303 0.319 l 0.50 0.80 0.020 0.031 0 10 0 10 n8 8 cp 0.10 0.004 so-b e n cp b e a2 d c l a1 h a 1
package mechanical m24512-w, m24512-r 26/31 figure 13. so8n ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 16. so8n ? 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 ddd 0.10 0.004 e 3.80 4.00 0.150 0.157 e1.27? ?0.050? ? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 so-a e 8 ddd b e a d c l a1 1 h h x 45? a2
m24512-w, m24512-r package mechanical 27/31 figure 14. tssop8 ? 8 lead thin shrink small outline, package outline 1. drawing is not to scale. table 17. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 n8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
part numbering m24512-w, m24512-r 28/31 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 18. ordering information scheme example: m24512 ? w mw 6 t p device type m24 = i 2 c serial access eeprom device function 512 = 512 kbit (64k x 8) operating voltage w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v package mw = so8 (208 mil width) mn = so8 (150 mil body width) dw = tssop8 device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p or g = ecopack? (rohs compliant)
m24512-w, m24512-r revision history 29/31 9 revision history table 19. document revision history date revision changes 29-jan-2001 1.1 lead soldering temperature in the absolute maximum ratings table amended write cycle polling flow chart using ack illustration updated lga8 and so8(wide) packages added references to psdip8 changed to pdip8, and package mechanical data updated 10-apr-2001 1.2 lga8 package mechanical data and illustration updated so16 package removed 16-jul-2001 1.3 lga8 package given the designator ?la? 02-oct-2001 1.4 lga8 packag e mechanical data updated 13-dec-2001 1.5 document becomes preliminary data test conditions for ili, ilo, zl and zh made more precise vil and vih values unified. tns value changed 12-jun-2001 1.6 document promoted to full datasheet 22-oct-2003 2.0 table of contents, and pb-free opti ons added. minor wording changes in summary description, power-on re set, memory addressing, write operations, read operations. v il (min) improved to ?0.45v. 02-sep-2004 3.0 lga8 package is not for new design. 5v and -s supply ranges, and device grade 5 removed. abso lute maximum ratings for v io (min) and v cc (min) changed. soldering temperature information clarified for rohs compliant devices. device grade information clarified. aec-q100-002 compliance. v il specification unified for sda, scl and wc
revision history m24512-w, m24512-r 30/31 22-feb-2005 4.0 initial delivery state is ffh (not necessarily the same as erased). lga package removed, tssop8 and so8n packages added (see package mechanical section and table 18., ordering information scheme). voltage range r (1.8v to 5.5v) also offered. minor wording changes. z l test conditions modified in table 10., input parameters and note 3. added. i cc and i cc1 values for v cc = 5.5v added to table 11., dc characteristics (m24512-w). note added to table 11., dc characteristics (m24512-w). power on reset paragraph specified. t w max value modified in table 13., ac characteristics (m24512- w) and note 4 added. plating technology changed in table 18., ordering information scheme. resistance and capacitance renamed in figure 4., maximum r p value versus bus parasitic capacitance (c) for an i 2 c bus. 05-may-2006 5 power on reset paragraph replaced by section 2.5: supply voltage (v cc ) . figure 3: device select code added. write cycling added and specified at 1 million cycles. i cc0 added and i cc1 specified over the whole voltage range in ta b l e 1 1 and ta bl e 1 2 . pdip8 package removed. packages are ecopack? compliant. small text changes. table 19. document revision history (continued) date revision changes
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